(1) Field of the Invention
The present invention relates to a voltage-variable capacitor (varactor) used for a radio frequency (RF) circuit such as a voltage-controlled oscillator, and more particularly relates to a MIS capacitor fabricated using an existing CMOS process.
(2) Description of Related Art
Varactors that are voltage-variable capacitors have conventionally been widely used for many radio frequency (RF) circuits. One of known devices for realizing varactors is a device utilizing the depletion layer capacitance of a PN junction, more specifically a varactor diode.
Tuning ratio (TR) representing the ratio between the capacitance C2 at a reverse bias voltage of zero and the capacitance C1 at a predetermined reverse bias voltage is often used as an index for evaluating performance of varactors. Larger tuning ratio (C2/C1) allows significant change in the varactor capacitance even within the same gate voltage width. Thus, the controllable resonant frequency range of an antenna becomes wider.
FIG. 13 is a graph showing the bias dependence of the capacitance of a PN diode. The increase in reverse bias Vg increases the width of the depletion layer in the PN diode. Thus, the capacitance C1 decreases. The width of the depletion layer depends on the concentration of P-type and N-type impurities. Hence, the width of the depletion layer becomes narrower with increase in doping amount, resulting in the increased capacitance of the PN diode.
In recent years, smaller circuits are being highly demanded, and thus it has been desired to mount a varactor and a CMOS device on one chip. Therefore, existing CMOS process are used to form MIS capacitors serving as varactors.
FIG. 14 is a cross-sectional view showing the structure of a known semiconductor device in which a CMOS device and a varactor (MIS capacitor) are mounted on a common substrate.
As shown in this figure, the known semiconductor device includes an STI (Shallow Trench Isolation) structure partitioning the surface of a semiconductor substrate 100 that is a Si substrate into a plurality of active regions. The plurality of active regions comprise transistor regions Tr to be formed with MISFETs of the CMOS device and varactor regions Va to be formed with varactors. Although the MISFETs of the CMOS device include an NMISFET and a PMISFET, this figure shows only a region of the semiconductor device to be formed with an NMISFET.
The semiconductor substrate 110 is formed with a P well region 111 doped with a P-type impurity and an N well region 112 obtained by doping a part of the P well region 111 with an N-type impurity. The N well region 112 shown in FIG. 14 is an active region for a varactor. A gate dielectric 116 of a silicon oxide film, a polysilicon gate electrode 118 doped with an N-type impurity, a sidewall 117 of a silicon oxide film are provided on the semiconductor substrate 110 in each of the varactor region Va and the transistor region Tr. Parts of the N well region 112 located to both sides of the polysilicon gate electrode 118 in the varactor region Va are formed with substrate contact impurity diffusion regions 113a doped with an N-type impurity at a relatively high concentration and extension regions 113b doped with an N-type impurity at an intermediate concentration. Parts of the P well region 111 located to both sides of the polysilicon gate electrode 118 in the transistor region Tr are formed with high-concentration source/drain regions 114a doped with an N-type impurity at a relatively high concentration and extension regions 114b doped with an N-type impurity at an intermediate concentration. Each of the varactor region Va and the transistor region Tr is formed with an on-gate silicide layer 115a and on-diffusion-region silicide layers 115b through a salicide process.
Briefly speaking, the structure of the semiconductor device shown in FIG. 14 is formed through the following fabricating process steps. First, an STI structure, a P well region 111 and an N well region 112 are formed in a semiconductor substrate 110. Then, a common gate dielectric 116 and a common polysilicon gate electrode 118 are formed in each of a varactor region Va and a transistor region Tr. Thereafter, N-type impurity ions are implanted into the N well region 112 and the P well region 111 at an intermediate concentration by using the polysilicon gate electrodes 118 as masks to form extension regions 113b and 114b. Next, a silicon oxide film is deposited on the substrate, and thereafter anisotropic etching is performed to form sidewalls 117 covering the sides of the polysilicon gate electrodes 118. Furthermore, impurity ions are implanted into the N well region 112 and the P well region 111 at a relatively high concentration by using the polysilicon gate electrode 118 and the sidewall 117 as masks, thereby forming substrate contact impurity diffusion regions 113a in the varactor region Va and high-concentration source/drain regions 114a in the transistor region Tr. Thereafter, both the varactor region Va and the transistor region Tr are subjected to a salicide process to form an on-gate silicide layer 115a on each polysilicon gate electrode 118 and an on-diffusion-layer silicide layer 115b on each of the substrate contact impurity diffusion regions 113a and the high-concentration source/drain regions 114a. 
With the structure of the semiconductor device shown in FIG. 14, each of members in the varactor region Va can be formed by utilizing the existing process for fabricating a CMOS device.